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femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer ICS843003I-09 idt? / ics? 3.3v lvpecl frequency synthesizer 1 ics843003bgi-09 rev. a april 17, 2008 general description the ICS843003I-09 is a 3 differential output lvpecl synthesizer designe d to generate ethernet reference clock frequencies and is a member of the hiperclocks? family of high performance clock solutions from idt. using a 25mhz, 18pf parallel resonant crystal, the following frequencies can be generated: 156.25mhz and 125mhz. the 843003 i-09 has two output banks, bank a with one differential lvpecl output pair and bank b with two differential lvpec l output pairs. the ICS843003I-09 uses idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter requirements. the ICS843003I-09 is packaged in a small 24-pin tssop, epad package. features ? three 3.3vdifferential lvpecl output pairs on two banks: bank a with one lvpecl output pair bank b with two l vpecl output pairs ? selectable crystal oscillator interface or lvcmos/lvttl single-ended reference clock input ? vco range: 490mhz ? 680mhz ? rms phase jitter @ 156.25m hz (1.875mhz ? 20mhz): 0.53ps (typical) ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages block diagram hiperclocks? ic s 0 1 0 1 phase detector vco 25 4 5 osc qa0 nqa0 qb0 nqb0 qb1 nqb1 oea vco_sel ref_clk xtal_sel xtal_out xtal_in mr oeb pullup pullup pulldown pulldown pullup pullup 25mhz pin assignment ICS843003I-09 24-lead tssop, epad 4.4mm x 7.8mm x 0.9mm package body g package top view 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nc vco_sel mr v cco_a qa0 nqa0 oeb oea nc v cca v cc nc nc v cco_b nqb0 qb0 nqb1 qb1 xtal_sel ref_clk xtal_in xtal_out v ee nc
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 2 ics843003bgi-09 rev. a april 17, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 9, 12, 13, 24 nc unused no connect. 2 vco_sel input pullup vco select pin. when low, the pll is bypassed and the crystal reference or ref_clk (depending on xtal_sel setting) are passed directly to the output dividers. has an internal pullup re sistor so the pll is not bypassed by default. lvcmos/lvttl interface levels. 3 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qx to go low and the inverted outputs nqx to go high. when logic low, the internal di viders and the outputs are enabled. mr has an internal pulldown resistor so t he power-up default state of the outputs and dividers are enabled. lvcmos/lvttl interface levels. 4v cco_a power output supply pin for bank a outputs. 5, 6 qa0, nqa0 output differential output pair. lvpecl interface levels. 7 oeb input pullup bank b output enable pin. active high output enable. when logic high, the 2 output pairs on bank b are enabled. w hen logic low, the output pairs drive differential low (qbx = low, nqbx = high). oeb has an internal pullup resistor so the default power-up state of outputs are enabled. lvcmos/lvttl interface levels. 8 oea input pullup bank a output enable pin. active high output enable. when logic high, the output pair on bank a is enabled. when logic low, the output pair drives differential low (qa0 = low, nqa0 = high). oea has an internal pullup resistor so the default power-up state of outputs are enabled. lvcmos/lvttl interface levels. 10 v cca power analog supply pin. 11 v cc power core supply pin. 14 v ee power negative supply pin. 15, 16 xtal_out, xtal_in input parallel resonant crystal interface. xtal_out is the output, xtal_in is the input. 17 ref_clk input pulldown single-ended reference clock input. lvcmos/lvttl interface levels. 18 xtal_sel input pullup crystal select pin. selects between the single-ended ref_clk or crystal interface. has an internal pullup resistor so the crystal interface is selected by default. lvcmos/lvttl interface levels. 19, 20 nqb1, qb1 output differential output pair. lvpecl interface levels. 21, 22 nqb0, qb0 output differential output pair. lvpecl interface levels. 23 v cco_b power output supply pin for bank b outputs. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 3 ics843003bgi-09 rev. a april 17, 2008 function tables table 3a. bank a frequency table table 3b. bank b frequency table table 3c. oea select function table table 3d. oeb select function table figure 1. oe timing diagram input feedback divider bank a output divider m/n multiplication factor qa0/nqa0 output frequency (mhz) crystal frequency (mhz) 25 25 4 6.25 156.25 24 25 4 6.25 150 20 25 4 6.25 125 input feedback divider bank b output divider m/n multiplication factor qb[0:1]/nqb[0:1] output frequency (mhz) crystal frequency (mhz) 25 25 5 5 125 input outputs oea qa0 nqa0 0lowhigh 1 active active input outputs oeb qb0, qb1 nqb0, nqb1 0lowhigh 1 active active enabled disabled ref_clk oea, oeb nqa0, nqb0, nqb1 qa0, qb0, qb1
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 4 ics843003bgi-09 rev. a april 17, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma package thermal impedance, ja 32.1 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.20 3.3 3.465 v v cco_a, v cco_b output supply voltage 3.135 3.3 3.465 v i ee power supply current 150 ma i cca analog supply current 20 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current mr, ref_clk v cc = v in = 3.465v 150 a oea, oeb, vco_sel, xtal_sel v cc = v in = 3.465v 5 a i il input low current mr, ref_clk v cc = 3.465v, v in = 0v -5 a oea, oeb, vco_sel, xtal_sel v cc = 3.465v, v in = 0v -150 a
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 5 ics843003bgi-09 rev. a april 17, 2008 table 4c. lvpecl dc characteristics, v cc = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco_a, _b ? 2v. table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. ac electrical characteristics table 6. ac characteristics, v cc = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: please refer to the phase noise plots. note 2: defined as skew within a bank of outputs at the same voltage and with equal load conditions. symbol parameter test conditions minimum typical maximum units v oh output high current; note 1 v cco_a/b ? 1.4 v cco_a/b ? 0.9 a v ol output low current; note 1 v cco_a/b ? 2.0 v cco_a/b ? 1.7 a v swing peak-to-peak output voltage swing 0.6 1.0 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 19.6 27.2 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf drive level 1mw parameter symbol test conditio ns minimum typical maximum units f out output frequency range 4 122.5 170 mhz 5 98 136 mhz t jit(?) rms phase jitter, (random); note 1 156.25mhz, (1.875mhz ? 20mhz) 0.53 ps 125mhz, (1.875mhz ? 20mhz) 0.48 ps t sk(b) bank skew; note 2 50 ps t r / t f output rise/fall time 20% to 80% 200 600 ps odc output duty cycle 45 55 %
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 6 ics843003bgi-09 rev. a april 17, 2008 typical phase noise at 156.25mhz 10 gigabit ethernet filter phase noise result by adding a 10 gigabit ethernet filter to raw data raw phase noise data ? ? ? 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.53ps (typical) noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m offset frequency (hz)
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 7 ics843003bgi-09 rev. a april 17, 2008 parameter measureme nt information 3.3v lvpecl output load ac test circuit bank skew output duty cycle/pulse width/period rms phase jitter output rise/fall time scope qx nqx lvpecl v ee v cc, 2v% 1.3v 0.165v - v cca v cco_a, v cco_b 2v% nqb0 qb0 nqb1 qb1 t sk(b) t pw t period t pw t period odc = x 100% nqa0, nqb0, nqb1 qa0, qb0, qb1 - phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 20% 80% 80% 20% t r t f v swing nqa0, nqb0, nqb1 qa0, qb0, qb1
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 8 ics843003bgi-09 rev. a april 17, 2008 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ICS843003I-09 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc, v cca, v cco_b and v cco_b should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 2 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v cca pin. figure 2. power supply filtering recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. ref_clk input for applications not requiring the us e of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. v cc v cca 3.3v 10 ? 10f .01f .01f
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 9 ics843003bgi-09 rev. a april 17, 2008 crystal input interface the ICS843003I-09 has been characterized with 18pf parallel resonant crystals. the ca pacitor values shown in figure 3 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to mi nimize the ppm error. figure 3. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 4. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 4. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 22p c2 22p xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v cc v cc
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 10 ics843003bgi-09 rev. a april 17, 2008 termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 11 ics843003bgi-09 rev. a april 17, 2008 epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadfame base package, amkor technology. figure 6. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 12 ics843003bgi-09 rev. a april 17, 2008 power considerations this section provides information on power dissipati on and junction temperature for the ICS843003I-09. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS843003I-09 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 150ma = 519.75mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 3 * 30mw = 90mw total power_ max (3.3v, with all outputs switching) = 519.75mw + 90mw = 609.75mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.610w * 32.1c/w = 104.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 7. thermal resistance ja for 24 lead tssop, epad forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 32.1c/w 25.5c/w 24c/w
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 13 ics843003bgi-09 rev. a april 17, 2008 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cco - 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v for logic low, v out = v ol_max = v coo_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max ))/r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max ))/r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 14 ics843003bgi-09 rev. a april 17, 2008 reliability information table 8. ja vs. air flow table for a 24 lead tssop, epad transistor count the transistor count for ICS843003I-09 is: 3822 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 32.1c/w 25.5c/w 24c/w
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 15 ics843003bgi-09 rev. a april 17, 2008 package outline and package dimensions package outline - g suffix for 24 lead tssop, epad table 9. package dimensions reference document: jedec publication 95, mo-153 all dimensions in millimeters symbol minimum nominal maximum n 24 a 1.10 a1 0.05 0.15 a2 0.85 0.90 0.95 b 0.19 0.30 b1 0.19 0.22 0.25 c 0.09 0.20 c1 0.09 0.127 0.16 d 7.70 7.90 e 6.40 basic e1 4.30 4.40 4.50 e 0.65 basic l 0.50 0.60 0.70 p 5.0 5.5 p1 3.0 3.2 0 8 0.076 bbb 0.10
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? 3.3v lvpecl frequency synthesizer 16 ics843003bgi-09 rev. a april 17, 2008 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843003bgi-09 ics843003bi09 24 lead tssop, e-pad tube -40 c to 85 c 843003bgi-09t ics843003bi09 24 lead tsso, epad 2500 tape & reel -40 c to 85 c 843003bgi-09lf ics43003bi09l ?lead-fr ee? 24 lead tssop, epad tube -40 c to 85 c 843003bgi-09lft ics43003bi09l ?lead-free? 24 lead tssop, epad 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applicat ions, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ICS843003I-09 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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